Araña - An Alpha Microprocessor Designed for High Performance

Guest Speaker: Dr. Trigve Fossum
Intel Fellow, Enterprise Platforms Group
Director, Microarchitecture Development
Massachusetts Microprocessor Design Center

October 25, 2002
11 a.m. - 12 noon
Fuller Labs 320

Abstract

In this presentation, I describe an Alpha microprocessor design done at Digital and Compaq to achieve record levels of performance. The talk will deal with out- of-order execution, wide superscalar instruction issue, and Simultaneous Multi Threading. I will discuss some of the new micro architectural problems encountered in a design targeted to high levels of Instruction Level Parallelism.

Biography

Tryggve Fossum is an Intel Fellow, Enterprise Platforms Group, and Director, Microarchitecture Development at the Massachusetts Microprocessor Design Center. He leads the team of architects developing the next generation of Intel^® Itanium^TM processors.

Prior to joining Intel, Fossum held a variety of positions during 28 years of combined service to Compaq and Digital Equipment Corporation. Since 1998, he has served as a Compaq Fellow and was lead architect for future versions of the Alpha microprocessor.

Fossum received a Cand. Mag. degree in Science from the University of Oslo in 1968. He earned his doctorate and master's degree in mathematics from the University of Illinois in 1972 and 1970, respectively. Fossum completed a post- doctorate program at the University of Illinois in 1973. He holds 27 patents on various aspects of computer design.

Refreshments will be served in FL 320 beginning at 10:50 a.m.

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