A New Approach to Security Processing (SSL and IPsec)

Anil Jain
VP of IC Engineering
Co-Founder of Cavium Networks

November 15, 2002
11 a.m. - 12 noon
Fuller Labs 320

Abstract

First generation security solutions only provided hardware acceleration of the cryptographic algorithms such as DES/3DES, SHA-1/MD5, and modular exponentiation.

Second generation security solutions targeted at SSL and IPsec combined many of the crypto algorithms into a single ASIC. These solutions addressed only parts of the security needs.

Cavium Network's 3rd genration Nitrox Security Macro Processor provides a single chip, programmable solution for SSL and IPsec based applications. The Nitrox chip performs symmetric and asymmetric processing, packet parsing, and minimizes bus traffic between the host and co-processor to deliver a complete security solution. The chip is implemented in a 0.13um CMOS process and contains 65 million transistors.

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