The SCALE Project

Dr. Krste Asanovic
MIT

April 18, 2003
11 a.m. - 12 noon
Fuller Labs 320

Abstract

The SCALE (Software-Controlled Architectures for Low Energy) project is developing a new "all-purpose" VLSI architecture for future embedded and general-purpose systems. Despite the ample parallelism present in many applications, existing processors are hampered by legacy serial instruction sets and can only execute a handful of instructions per cycle. SCALE introduces a new parallel instruction set paradigm, vector threading, which supports many forms of fine-grain parallelism from pure SIMD data parallelism to pure MIMD thread parallelism, at low cost and low power dissipation. For many applications, power consumption will be the primary constraint on system performance, cost, and size. A major emphasis in the SCALE project is the development of new techniques that give software fine-grain control over processor energy usage. By exposing hardware energy consumption to software, we can exploit compile-time knowledge to reduce run-time energy dissipation. This talk will present an verview of the SCALE project and the design of the SCALE-0 microprocessor prototype which is underway at MIT.

Biography

Krste Asanovic received a B.A. in Electrical and Information Sciences from Cambridge University in 1987 and a Ph.D. in Computer Science from UC Berkeley in 1998. He is an Associate Professor in the MIT Department of Electrical Engineering and Computer Science and a member of the MIT Laboratory for Computer Science. At MIT, he leads the SCALE project which is developing new energy efficient microprocessor architectures.

Host

Prof. Neil Hefferman

Refreshments will be served.

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Last modified: Sep 27, 2006, 16:05 EDT