Sample Microarchitecture

General Registers:

ACC

(Register 0) Accumulator

PC

(Register 1) Program counter

IR

(Register 2) Instruction register

TMP

(Register 3) Temporary register, used for instruction decoding, among other things

AMASK

(Register 4) Address mask, used to mask out the high-order bits of an instruction, leaving the 13 address bits

1

(Register 5) Contains the constant 1

Other Registers:

MAR

Memory address register

MBR

Memory buffer register

MIR

Microprogram instruction register

MPC

Microprogram program counter

The Instruction Set:

Note: Instructions in the machine language are 16 bits: the high-order 3 bits comprise the opcode, the low-order 13 bits comprise the address.

Instruction	Op code	Description
ADD	000	ACC := ACC + (A)
SUB	001	ACC := ACC - (A)
LOAD	010	ACC := (A)
STORE	011	(A) := ACC
JUMP	100	PC := A
JZER	101	If ACC==0 JUMP A

The Microprogram

 0:  MAR := PC; READ;                               // gets low-order 13 bits
 1:  READ;                                          // data returned in MBR
 2:  PC := PC + 1;
 3:  IR := MBR;  if N then goto 25                  // check bit 0 of opcode
 4:  TMP := lshift(IR + IR); if N then goto 16      // check bit 1
 5:  TMP := TMP; if N then goto 10;                 // check bit 2

 6:  MAR := IR; READ;                               // ADD (000)
 7:  READ;
 8:  ACC := MBR + ACC;
 9:  goto 0;

10:  MAR := IR; READ;                               // SUB (001)
11:  READ;
12:  ACC := ACC + 1;
13:  TMP := com(MBR);                               // 1's complement
14:  ACC := ACC + TMP;
15:  goto 0;

16:  TMP := TMP; if N then goto 21                  // check bit 2
17:  MAR := IR; READ;                               // LOAD (010)
18:  READ;
19:  ACC := MBR;
20:  goto 0;

21:  MAR := IR;                                     // STORE (011)
22:  MBR := ACC; WRITE;
23:  WRITE;
24:  goto 0;

25:  TMP := lshift(IR+IR); if N then goto 0;       // No opcodes 11...
26:  TMP := TMP; if N then goto 29

27:  PC := and(IR, AMASK);                         // JUMP (100)
28:  goto 0;

29:  ACC := ACC; if Z then goto 27;                // JZER (101)
30:  goto 0;

Notes:

• MAR is 13 bits wide
• The ALU has 4 functions: addition (+), binary and (and), complement left operand (com), and pass left operand through unchanged (default)
• The shifter allows for a left shift (lshift), right shift (rshift), or no shift (default). Shifting occurs after data has passed through the ALU (and after the ALU status bits have been set).
• Two latches A and B are used to present stable data to the ALU. This is necessary for operations in which the same register is used for both the input and the output of a single operation; there can be no mixture of bits. (The ALU is a circuit which continually computes the inputs. The ALU needs to be shielded from changes to busses as new values are being stored in the scratchpad:

  A = A + B
      ^
      This must be the original value, not some mixture of bits from old and
      new computed values
  

• A store into a general register is denoted by an assignment statement.
• The ALU outputs two status bits: N if the ALU output is negative (leftmost bit==1), and Z if the ALU output is zero.
• READ and WRITE take two micro-instruction cycles
• the control store is a 64x27-bit read-only memory. The format of each microinstruction (and the number of bits in each field) is as follows:

MUX	COND	ALU	SH	MBR	MAR	RD	WR	ST	C	B-latch	A-latch	ADDR
1	2	2	2	1	1	1	1	1	3	3	3	6

MUX

(0) left ALU input is A-latch, (1) left ALU input is MBR

COND

(00) no jump, (01) jump if N=1, (10) jump if Z=1, (11) unconditional jump

ALU

(00) +, (01) and, (10) pass, (11) com

SH

(00) no shift, (01) left, (10) right, (11) not used

MBR

(0) don't put result in MBR, (1) put result in MBR

MAR

(0) don't put result in MAR, (1) put result in MAR

RD

(0) don't read, (1) read

WR

(0) don't write, (1) write

ST

(0) don't store result in general register, (1) store result in general register (register selected by field C)

C

register selected for storing

B-latch

number of right ALU input

A-latch

number of left ALU input

ADDR

address of potential successor to current microinstruction (if COND=00, next microinstruction is MPC+1)

References

1.

De Blasi, Mario, Computer Architecture, Addison Wesley, 1990, (Chapter 7)

2.

Deitel, Harvey M., An Introduction to Operating Systems, Addison Wesley, 1984, (Chapter 2)

3.

Tanenbaum, Andrew S., Structured Computer Organization, 3rd edition, Prentice Hall, 1990, (Chapter 4)